Some example embodiments of the inventive concepts disclosed herein relate to semiconductor devices, and more particularly, to storage devices for performing data training at high speed and/or data training methods thereof.
Data training (or DQ training) is desired to secure reliability of data in a storage device implemented with a plurality of nonvolatile memory devices and a controller. The data training includes read training and write training. The read training refers to an operation in which the controller aligns the center of an eye pattern of data Dout output from a nonvolatile memory device. The write training refers to an operation for aligning an eye pattern of data Din to be written in a nonvolatile memory device.
For the data training, the controller may write data of a specific pattern in respective nonvolatile memory devices or may read data of a specific pattern from a nonvolatile memory device. Because a command and an address for the purpose of writing or reading pattern data in a nonvolatile memory device needs to be inputted, a time to input a command and an address and to input or output pattern data and a time for AC timing are inevitably taken to perform the data training.
According to needs for a high-speed and high-capacity storage device, a storage device is desired to include more nonvolatile memory devices as a storage medium and provide a speedier response characteristic. In the storage device including the large number of nonvolatile memory devices, it is desired to reduce open timing for the purpose of providing speedy access performance in a situation such as power-up. Thus, a technology for reducing the open timing, (e.g., a time taken for the data training) is desired.